ut std_logic);
end par_ser;
architecture rtl of par_ser is
signal tmp:std_logic;
signal reg:std_logic_vector(7 downto 0);
begin
process(clk,load)
begin
if(clk'event and clk='1') then
if(load='1') then
reg<=par_in;
busy<='1';
end if;
if(tmp='1') then
busy<='0';
end if;
end if;
end process;
process(clk)
variable count:integer;
variable oreg:std_logic_vector(8 downto 0);
begin
if(clk'event and clk='1') then
if(busy='1') then
count:=0;
oreg:=reg & '0'; --reg左移一位
ser_out<=oreg(0);
tmp<='0';
end if;
for i in 0 to 7 loop
if(clk'event and clk='1') then
oreg:='0'&oreg((7+i) downto i); --oreg右移一位
ser_out<=oreg(0);
--count:=count-1;
end if;
end loop;
if(clk'event and clk='1') then
tmp<='1';
end if;
end if;
end process;
end rtl;| 欢迎光临 电子技术论坛_中国专业的电子工程师学习交流社区-中电网技术论坛 (http://bbs.eccn.com/) | Powered by Discuz! 7.0.0 |