always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
State <= Idle;
k1 <=1'b0;
k2 <=1'b0;
end
else case (State) //状态判断与组合逻辑赋值
Idle :if(A) begin
State <= Start;
k1 <= 0;
end
else begin
State <= Idle;
k1 <= 0;
k2 <= 0;
end
Start :if(!A) State <= Stop;
else State <= Start;
Stop :if(A) begin
State <=Clear;
k2 <= 1;
end
else State <= Stop;
Clear :if(!A) begin
State <= Clear;
k2 <= 0;
k1 <= 1;
end
else State <= Clear;
default : State <= 2'bxx; //告诉综合器 case语句已经指定了所有状态,这样综合器就会删除不需要的译码电路,使生成的电路简单
endcase
endmodule
//************************小墨品牌,你值得拥有~**************************