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标题: UART VHDL源程序-1 [打印本页]

作者: 苹果也疯狂 时间: 2015-2-26 20:20 标题: UART VHDL源程序-1

-- This Design Implements A UART.

--    Version 1.1 : Original Creation

--    Version 1.2 : Modified To Std_logic Types

--    Version 2.1 : Extended Reset To Be More Effective.

--    Introduced OTHERS Clause.

------------------------------------------------------------------

LIBRARY Ieee;

Use Ieee.Std_logic_1164.All;

Use Ieee.Std_logic_arith.All;

Use Ieee.Std_logic_unsigned.All;

ENTITY Uart IS

PORT (Clkx16 : IN Std_logic; -- Input Clock. 16x Bit Clock

         Read : IN Std_logic; -- Received Data Read Strobe

         Write : IN Std_logic; -- Transmit Data Write Strobe

   Rx : IN Std_logic; -- Receive  Data Line

Reset : IN Std_logic; -- Clear Dependencies

   Tx : OUT Std_logic; -- Transmit Data Line

         Rxrdy : OUT Std_logic; -- Received Data Ready To Be Read

         Txrdy : OUT Std_logic; -- Transmitter Ready For Next Byte

   Parityerr : OUT Std_logic; -- Receiver Parity Error

   FRAMingerr : OUT Std_logic; -- Receiver Framing Error

      Overrun : OUT Std_logic; -- Receiver Overrun Error

   Data : INOUT Std_logic_vector(0 TO 7)); -- Bidirectional Data Bus

END Uart;

ARCHITECTURE Exemplar OF Uart IS

-- Transmit Data Holding Register

SIGNAL    Txhold : Std_logic_vector(0 TO 7);

-- Transmit Shift Register Bits

SIGNAL    Txreg : Std_logic_vector(0 TO 7);

SIGNAL    Txtag2 : Std_logic; -- Tag Bits For Detecting

SIGNAL    Txtag1 : Std_logic; -- Empty Shift Reg

SIGNAL Txparity : Std_logic; -- Parity Generation Register

-- Transmit Clock And Control Signals

SIGNAL    Txclk : Std_logic;    -- Transmit Clock: 1/16th Of Clkx16

SIGNAL    Txdone : Std_logic; -- ''1'' When Shifting Of Byte Is Done

SIGNAL Paritycycle : Std_logic; -- ''1'' On Next To Last Shift Cycle

SIGNAL Txdatardy : Std_logic;    -- ''1'' When Data Is Ready In Txhold

-- Receive Shift Register Bits

SIGNAL    Rxhold : Std_logic_vector(0 TO 7);-- Holds Received Data For Read

SIGNAL    Rxreg : Std_logic_vector(0 TO 7);-- Receive Data Shift Register

SIGNAL Rxparity : Std_logic; -- Parity Bit Of Received Data

SIGNAL Paritygen : Std_logic; -- Generated Parity Of Received Data

SIGNAL    Rxstop : Std_logic; -- Stop Bit Of Received Data

-- Receive Clock And Control Signals

SIGNAL    Rxclk : Std_logic; -- Receive Data Shift Clock

SIGNAL    Rxidle : Std_logic;    -- ''1'' When Receiver Is Idling

SIGNAL Rxdatardy : Std_logic;    -- ''1'' When Data Is Ready To Be Read

BEGIN

Make_txclk:

PROCESS (Reset, Clkx16)

VARIABLE Cnt  : Std_logic_vector(2 DOWNTO 0);

BEGIN

-- Toggle Txclk Every 8 Counts, Which Divides The Clock By 16

IF Reset=''1'' THEN

   Txclk <= ''0'' ;

   Cnt := (OTHERS=>''0'') ;

ELSIF Clkx16''Event AND Clkx16=''1'' THEN

   IF (Cnt = "000") THEN

      Txclk <= NOT Txclk;

   END IF;

   Cnt := Cnt + "001"; -- Use The Exemplar_1164 "+" On Std_logic_vector

END IF;

END PROCESS;

Make_rxclk:

PROCESS  (Reset, Clkx16)

VARIABLE Rxcnt : Std_logic_vector(0 TO 3); -- Count Of Clock Cycles

VARIABLE Rx1 : Std_logic; -- Rx Delayed One Cycle

VARIABLE Hunt  : Boolean; -- Hunting For Start Bit

BEGIN

IF Reset=''1'' THEN

   -- Reset All Generated Signals And Variables

   Hunt := FALSE ;

   Rxcnt := (OTHERS=>''0'') ;

   Rx1 := ''0'' ;

   Rxclk <= ''0'' ;

ELSIF Clkx16''EVENT AND Clkx16 = ''1'' THEN

   -- Rxclk = Clkx16 Divided By 16

   Rxclk <= Rxcnt(0);

   -- Hunt=TRUE When We Are Looking For A Start Bit:

   --  A Start Bit Is Eight Clock Times With Rx=0 After A Falling Edge

   IF (Rxidle = ''1'' AND Rx = ''0'' AND Rx1 = ''1'') THEN

            -- Start Hunting When Idle And Falling Edge Is Found

      Hunt := TRUE;

   END IF ;

   IF Rxidle = ''0'' OR Rx = ''1'' THEN

      -- Stop Hunting When Shifting In Data Or A 1 Is Found On Rx

      Hunt := FALSE;

   END IF;

   Rx1 := Rx; -- Rx Delayed By One Clock For Edge Detection

-- (Must Be Assigned AFTER Reference)

   -- Increment Count When Not Idling Or When Hunting

   IF (Rxidle = ''0'' OR Hunt) THEN

      -- Count Clocks When Not Rxidle Or Hunting For Start Bit

      Rxcnt := Rxcnt + "0001";

   ELSE

      -- Hold At 1 When Rxidle And Waiting For Falling Edge

      Rxcnt := "0001";

   END IF;

END IF ;

END PROCESS;

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