assign z = ( state==E && x==0 )? 1 : 0; //当x=0时,状态已变为E,
//状态为D时,x仍为1。因此
//输出为1的条件为( state==E && x==0 )。
always @(posedge clk)
if(!rst)
begin
state <= IDLE;
end
else
casex(state)
IDLE : if(x==1)
begin
state <= A;
end
A: if(x==0)
begin
state <= B;
end
B: if(x==0)
begin
state <= C;
end
else
begin
state <= F;
end
C: if(x==1)
begin
state <= D;
end
else
begin
state <= G;
end
D: if(x==0)
begin
state <= E;
end
else
begin
state <= A;
end
E: if(x==0)
begin
state <= C;
end
else
begin
state <= A;
end
F: if(x==1)
begin
state <= A;
end
else
begin
state <= B;
end
G: if(x==1)
begin
state <= F;
end
default:state=IDLE; //缺省状态为初始状态。
endcase
endmodule
测试模块源代码:
//------------------ seqdet.v -------------------
`timescale 1ns/1ns
`include "./seqdet.v"
module seqdet_Top;
reg clk,rst;
reg[23:0] data;
wire[2:0] state;
wire z,x;
assign x=data[23];
always #10 clk = ~clk;
always @(posedge clk)
data={data[22:0],data[23]};
initial
begin
clk=0;
rst=1;
#2 rst=0;
#30 rst=1;
data ='b1100_1001_0000_1001_0100;
#500 $stop;
end
seqdet m(x,z,clk,rst,state);
endmodule
仿真波形:
[[wysiwyg_imageupload:251:]] 练习:设计一个串行数据检测器。要求是:连续4个或4个以上的1时输出为1,其他输入情况下为0。编写测试模块并给出仿真波形。