FFG900 | 引脚分类 | 引脚个数 | 备注 |
PS IO | 128 | ARM处理系统的专用引脚 | |
Select IO | 362 | 普通的FPGA引脚 | |
Configuration Pins In Bank 0 | 17 | Jtag类的一些引脚 | |
GTX Pins | 16X4(16个通道,每通道两对差分引脚) | 高速串行收发引脚 | |
XADC Pins | 32 | 模数转换引脚 |
Pin Name | Type | Direction | Description |
DONE_0 | Dedicated | Bidirectional | 高有效,高代表配置完成 |
INIT_B_0 | Dedicated | Bidirectional | 低有效,表示配置存储器正在初始化 |
PROGRAM_B_0 | Dedicated | Input | 低有效,表示异步复位配置逻辑 |
TCK_0 | Dedicated | Input | Jtag时钟信号 |
TDI_0 | Dedicated | Input | Jtag数据输入 |
TDO_0 | Dedicated | Output | Jtag数据输出 |
TMS_0 | Dedicated | Input | Jtag模式选择 |
CFGBVS_0 | Dedicated | Input | 为bank0的配置引脚预选择电平标准,1表示bank0的供电电压为2.5或3.3;0表示bank0的供电电压为1.8 |
PUDC_B | Multi-function | Input | 上拉电阻配置引脚,配置Select IO在配置阶段或上电后的其上拉电阻是否使能。当接GND,表示不使能;接VCCO_34表示使能。 |
Pin Name | Type | Direction | Description |
GND | Dedicated | N/A | 地 |
VCCPINT | Dedicated | N/A | 1.0V,PS的供电电压 |
VCCUPAUX | Dedicated | N/A | 1.8V,PS的辅助电源 |
VCCO_MIO0 | Dedicated | N/A | 1.8—3.3,bank500中MIO的供电电压 |
VCCO_MIO0 | Dedicated | N/A | 1.8—3.3,bank501中MIO的供电电压 |
VCCO_DDR | Dedicated | N/A | 1.2V–1.8V,DDR的供电电压 |
VCC_PLL | Dedicated | N/A | 1.8V,PS的PLL供电电压,在它附近必须放置0.47uf—4.7uf的电容 |
VCCAUX | Dedicated | N/A | 1.8V,辅助电路供电电压 |
VCCAUX_IO_G# | Dedicated | N/A | 1.8或2.0V,辅助IO电路的供电电压 |
VCCINT | Dedicated | N/A | 内核逻辑的供电电压 |
VCCO_# | Dedicated | N/A | 每个bank的输出驱动电压 |
VCCBRAM | Dedicated | N/A | 1.0V,PL部分BLOCK RAM的供电电压 |
VCCBATT_0 | Dedicated | N/A | 关键存储器备用电源,若不使用,则接地 |
VREF | Multi-function | 门限电压 | |
RSVDVCC[3:1] | Dedicated | N/A | 保留引脚,必须接到VCCO_0 |
RSVDGND | Dedicated | N/A | 保留引脚,必须接地 |
Pin Name | Type | Direction | Description |
PS_POR_B | Dedicated | input | 上电复位引脚,必须保持低电平直到PS供电和CLK正常,当它为高后,PS开始自举(Boot) |
PS_CLK | Dedicated | Input | 系统时钟,必须在区间[30M,60M] |
PS_SRST_B | Dedicated | Input | 系统复位,0时强制PS进入复位状态 |
PS_MIO_VREF | Dedicated | 电压参考值 | 提供给RGMII的接收参考电压,其值等于1/2VCCO_MIO1 |
PS_MIO[53:0] | Multi-function | Input/Output | PS的多功能引脚,可被配置成SPI , Quad-SPI flash, NAND, USB, Ethernet, SDIO, UART, SPI, GPIO 接口 |
PS DDR Pins | |||
PS_DDR_CKP | Dedicated | Output | DDR差分时钟+ |
PS_DDR_CKN | Dedicated | Output | DDR差分时钟- |
PS_DDR_CKE | Dedicated | Output | DDR时钟允许 |
PS_DDR_CS_B | Dedicated | Output | DDR片选 |
PS_DDR_RAS_B | Dedicated | Output | DDR行有效信号 |
PS_DDR_CAS_B | Dedicated | Output | DDR列有效信号 |
PS_DDR_WE_B | Dedicated | Output | DDR写使能 |
PS_DDR_BA[2:0] | Dedicated | Output | DDR块地址 |
PS_DDR_A[14:0] | Dedicated | Output | DDR行或列地址 |
PS_DDR_ODT | Dedicated | Output | DDR终端控制引脚 |
PS_DDR_DRST_B | Dedicated | Output | DDR复位引脚 |
PS_DDR_DQ[31:0] | Dedicated | Input/Output | DDR数据线 |
PS_DDR_DM[3:0] | Dedicated | Output | DDR数据屏蔽信号 |
PS_DDR_DQS_P[3:0] | Dedicated | Input/Output | DDR数据选通信号+ |
PS_DDR_DQS_N[3:0] | Dedicated | Input/Output | DDR数据选通信号- |
PS_DDR_VRP | Dedicated | Output | DCI参考电压+,用来校准DDR的IO驱动强度,连接电阻后接地 |
PS_DDR_VRN | Dedicated | Output | DCI参考电压-,用来校准DDR的IO驱动强度,连接电阻后接VCCO_DDR |
PS_DDR_VREF[1:0] | Dedicated | Voltage Reference | DDR接口的参考电压 |
Pin Name | Type | Direction | Description |
VCCADC_0 | Dedicated | N/A | XADC模拟电路电源 |
GNDADC_0 | Dedicated | N/A | 模拟电路参考地 |
VP_0 | Dedicated | Input | 模拟差分输入正极 |
VN_0 | Dedicated | Input | 模拟差分输入负极 |
VREFP_0 | Dedicated | N/A | 1.2V参考电压 |
VREFN_0 | Dedicated | N/A | 参考地 |
AD0P through AD15P AD0N through AD15N | Multi-function | Input | 模拟输入端0--15 |
Pin Name | Type | Direction | Description |
MGTXRXP[0:3] or MGTPRXP[0:3] | Dedicated | Input | 差分接收端正极 |
MGTXRXN[0:3] or MGTPRXN[0:3] | Dedicated | Input | 差分接收端负极 |
MGTXTXP[0:3] or MGTPTXP[0:3] | Dedicated | Output | 差分发送端正极 |
MGTXTXN[0:3] or MGTPTXN[0:3] | Dedicated | Output | 差分发送端负极 |
MGTAVCC_G# | Dedicated | Input | 1.0V发送器和接收器的内部电路模拟供电电压 |
MGTAVTT_G# | Dedicated | Input | 1.2V发送驱动器的模拟供电电压 |
MGTVCCAUX_G# | 1.8V ,GTXE2发送器专用的Quad PLL辅助模拟供电电压 | ||
MGTREFCLK0/1P | 发送器的正参考时钟 | ||
MGTREFCLK0/1N | 发送器的负参考时钟 | ||
MGTAVTTRCAL | N/A | 内部电路校准用的精度参考电阻引脚 | |
MGTRREF | Input | 内部电路校准用的精度参考电阻引脚 |
Pin Name | Type | Direction | Description |
IO_LXXY_# IO_XX_# | Dedicated | Input/Output | 绝大多数IO都是差分的,但芯片顶端和低端的IO是单端的;#表示Bank号,XX表示该引脚在Bank里的序号,Y表示是P端还是N端 |
Device | I/Opins | SIO(Select IO) | PS IO | |
HR | HP | |||
XC7Z045 FFG900 | User IO | 212 | 150 | 128 |
Differential | 102 | 72 | -------- |
Pin Name | Type | Direction | Description |
MRCC | Multi-function | Input | multi-region Clock引脚,具有时钟功能的引脚,当时钟是单端时,时钟信号必须由MRCC引脚的正端输入 |
SRCC | Multi-function | Input | Single-region Clock引脚,具有时钟功能的引脚,当时钟是单端时,时钟信号必须由SRCC引脚的正端输入 |
VRN | Multi-function | N/A | DCI电压N型晶体管参考电阻引脚,应该在每一个Bank里接上参考电阻后上拉 |
VRP | Multi-function | N/A | DCI电压P型晶体管参考电阻引脚,应该在每一个Bank里接上参考电阻后下拉 |
DXP_0, DXN_0 | Dedicated | Input | 温敏二极管引脚,可用于检测芯片温度 |
T0, T1, T2, or T3 | Multi-function | Input | 存储器的字节分组 |
T0_DQS, T1_DQS, T2_DQS, or T3_DQS | Multi-function | Input | DDR的DQS使能引脚 |
欢迎光临 电子技术论坛_中国专业的电子工程师学习交流社区-中电网技术论坛 (http://bbs.eccn.com/) | Powered by Discuz! 7.0.0 |