我做的毕业设计是16位全加器的分析与设计,源程序已经写好了,用quartus软件检查过已经没错了,但就是不知道怎么可以仿真出波形来,希望高手帮忙/

最好能说明一下怎么看出毛刺,和怎么消除,谢谢了

源程序"

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER4 IS
  PORT(C4: IN STD_LOGIC;
       A4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       B4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       S4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
       CO4: OUT STD_LOGIC);
END ENTITY ADDER4;
ARCHITECTURE ART OF ADDER4 IS
  SIGNAL S5: STD_LOGIC_VECTOR(4 DOWNTO 0);
  SIGNAL A5, B5: STD_LOGIC_VECTOR(4 DOWNTO 0);
  BEGIN
    A5<='0'& A4;
    B5<='0'& B4;
    S5<=A5+B5+C4;
    S4<=S5(3 DOWNTO 0);
    CO4<=S5(4);
END ARCHITECTURE ART;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER16 IS          --由4位二进制并行加法器级联而成的16位二进制加法器
  PORT(C16: IN STD_LOGIC;
       A16: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
       B16: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
       S16: OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
       CO16: OUT STD_LOGIC);
END ENTITY ADDER16;
ARCHITECTURE ART OF ADDER16 IS
 COMPONENT ADDER4 IS      --对要调用的元件ADDER4B的界面端口进行定义
   PORT(C4: IN STD_LOGIC;
        A4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        B4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        S4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        CO4: OUT STD_LOGIC);
 END COMPONENT ADDER4;
 SIGNAL SC1, SC2, SC3: STD_LOGIC;    --4位加法器的进位标志
 BEGIN
    U1: ADDER4    --例化(安装)一个4位二进制加法器U1
     PORT MAP(C4=>C16, A4=>A16(3 DOWNTO 0), B4=>B16(3 DOWNTO 0),
     S4=>S16(3 DOWNTO 0), CO4=>SC1);
    U2: ADDER4    --例化(安装)一个4位二进制加法器U2
     PORT MAP(C4=>SC1, A4=>A16(7 DOWNTO 4), B4=>B16(7 DOWNTO 4),
     S4=>S16 (7 DOWNTO 4), CO4=>SC2);
    U3: ADDER4    --例化(安装)一个4位二进制加法器U1
     PORT MAP(C4=>SC2, A4=>A16(11 DOWNTO 8), B4=>B16(11 DOWNTO 8),
     S4=>S16(11 DOWNTO 8), CO4=>SC3);
    U4: ADDER4    --例化(安装)一个4位二进制加法器U1
     PORT MAP(C4=>SC3, A4=>A16(15 DOWNTO 12), B4=>B16(15 DOWNTO 12),
     S4=>S16(15 DOWNTO 12), CO4=>CO16);
END ARCHITECTURE ART;