如果没有用到多个BUS Master，典型如DMA，LCD控制器等都没有用到，具体看芯片，那么Matrix不会有什么性能提升；当然，如果用到了多个Slave，可能会有少量的性能损失，切换总线节点可能需要比直接仲裁更多的时间；（仲裁完成-传输数据 vs 仲裁完成-切换/保持总线节点-传输数据）
如果只用了一个Slave，比如Core，DMA，LCD都是只访问外部总线的SDRAM，实质上就是多主单从结构，效率或许会下降。
Bus matrix
The bus matrix connects the processor and debug interface to theexternal buses. The bus matrix interfaces to the following externalbuses:
ICode bus. This is for instruction and vector fetches from codespace. This is a 32-bit AHB-Lite bus.
DCode bus. This is for data load/stores and debug accesses tocode space. This is a 32-bit AHB-Lite bus.
System bus. This is for instruction and vector fetches, dataload/stores and debug accesses to system space. This is a 32-bitAHB-Lite bus.
PPB. This is for data load/stores and debug accesses to PPBspace. This is a 32-bit APB (v3.0) bus.
The bus matrix also controls the following:
Unaligned accesses. The bus matrix converts unaligned processoraccesses into aligned accesses.
Bit-banding. The bus matrix converts bit-band alias accessesinto bit-band region accesses. It performs:
bit field extract for bit-band loads
atomic read-modify-write for bit-band stores.
Write buffering. The bus matrix contains a one-entry writebuffer to decouple bus stalls from the processor core.
