31. “As a good design practice, never use gate delay to implement your delay logic under all circumstances”. Please tell me what does "gate delay"(闸) mean?(“一个好的设计, 在所有情况下都决不会使用门延迟来实现延迟逻辑. ”此处“门延迟”是什么意思?)
答: “By "gate delay" I mean using a series of logic gates to introduce certain amount of delay in the design. This is highly undesirable since gate delay changes with factors like temperature and process technology. The design may fail as temperature changes or using a different version silicon. Also designs relying on gate delay are not portable, meaning that you need to re-design the whole circuit whenever you want to change to another product series or part number, simply because the gate delay changes as well. (参考译文:“门延迟”指得是使用一系列逻辑门将一定数量的延迟导入到设计中. 既然门延迟更改像温度和处理技术这样的因素, 所以, 这是很不合适的. 由于温度的改变或使用不同版本的芯片, 设计可能会失败. 依赖门延迟的设计也不是可移植的, 也就是说, 要更改另一产品系列或部件号时, 需要重新设计整个电路, 只因为更改了门延迟. )
Always use fully synchronous design. You never need to reply on gate delay if your design is fully synchronous. (始终使用完全同步设计. 如果设计是全同步的, 则无需回应门延迟. )
32. This time I download another program to another chip SpartanII XC2S50PQ208 in another circuit, while it fails, and show the following message: ". . . Checking boundary-scan chain integrity. . . ERROR:JTag - Boundary-scan chain test failed at bit position '3' on instance '***'(a substitute for the real name of file). A problem may exist in the hardware configuration. Check that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage. ERROR:JTag - Boundary scan chain has been improperly specified. Please check your configuration and re-enter the boundary-scan chain information. Boundary-scan chain validated unsuccessfully. ERROR:JTag - : The boundary-scan chain has not been declared correctly. Verify the syntax and correctness of the device BSDL files, correct the files, reset the cable and retry this command. " With so many messages, I don't know what to do! I try many times but only fail, and doubt whether there is something wrong with the circuit?But the powers checked in circuit are right. Would you please give me some advice to crack the problem?(有一次, 将程序下载至SpartanII XC2S50PQ208芯片电路, 结果发生了故障, 并显示以下消息:“. . . Checking boundary-scan chain integrity. . . ERROR:JTag - Boundary-scan chain test failed at bit position '3' on instance '***'(实际的文件名)”. 问题可能在硬件配置. 检查了连线、扫描链路和电源接头都没有问题. 特定的扫描链路配置与实际的硬件相匹配, 电源充足且电压正常. “ERROR:JTag - Boundary scan chain has been improperly specified. Please check your configuration and re-enter the boundary-scan chain information. Boundary-scan chain validated unsuccessfully. ERROR:JTag - : The boundary-scan chain has not been declared correctly. Verify the syntax and correctness of the device BSDL files, correct the files, reset the cable and retry this command. ”这么多出错消息, 什么原因, 怎么办?)
答:Usually it is the result of a broken JTAG chain or noisy chain. Most commonly, the cable is not connected properly, a trace is not correct on the board, other devices in the chain are causing a problem, or a noisy parallel port exists. Try using a different PC. You can also add a 4. 7K pullup on the PROG pin of the FPGA and see if it helps. (通常, 这是由于中断的JTAG链或噪声链. 最常见的原因是, 连线不正确, 板子上的迹线不正确, 链路中的其它器件导致问题, 或者存在噪声并口. 试一下使用不同的PC. 也可以在FPGA的PROG引脚上增加一个4. 7K的上拉电阻, 看看是否有帮助. )
33. 在VHDL中, 定义为SIGNAL的量起到什么作用?什么时候需要定义这个量?下面的程序
ARCHITECTURE EXER2_ARCH OF EXERCISE2 IS
SIGNAL TEM: STD_LOGIC;
BEGIN
TEM<=PIN50 AND PIN51;
PIN8 <=TEM;
END EXER2_ARCH;
和如下的程序有何区别?
ARCHITECTURE EXER2_ARCH OF EXERCISE2 IS
BEGIN
PIN8<=PIN50 AND PIN51;
END EXER2_ARCH;
答:If PIN8 is declared in your port list, the 2 examples are identical. From a hardware design's perspective, you can think of a vhdl "signal" as an electrical signal. So basically you can declare every object as "signal". >From a simulation's perspective, there is a fundamental difference between "signal" and "variable" in vhdl. A variable is nothing more than an object that holds a value. A variable assignment occurs instantly in a vhdl simulation. Also, a variable can only exist within a process, so it cannot transfer values across processes. A signal, on the other hand, has a history of values. Whenever a signal assignment occurs, the vhdl simulator schedules an event to update the signal value after a certain period of simulation time - the signal does not get this new value instantly in the simulation time domain. Also, a signal can exists outside processes. Sounds complicated, but for most of the time you can simply use vhdl "signal" in your hardware design. (参考译文:如果在端口表中声明了PIN8, 这两个示例是一样的. 从硬件设计的角度看, 可以将vhdl "signal"视为电子信号. 因此, 基本上可以将每个对象声明为“signal”. 从仿真角度看, vhdl中的"signal" 与 "variable"是根本不同的. 变量只不过是拥有值的对象. 变量分配即时出现在vhdl仿真中. 而且, 变量只能存在于一个过程内, 因此它不能通过过程来传递值. 另一方面, 信号有多个值. 不论何时分配信号, vhdl仿真都会在某个仿真时段安排一个事件来更新信号的值. 在仿真时域里, 信号不会立即获得这个新的值. 而且信号可以存在于过程之外. 听起来好象有点复杂, 但大多数时候, 在硬件设计中可以只使用vhdl "信号". )
答:A simple answer is to use the BUFGMUX resource in Xilinx VirtexII devices. The BUFGMUX is actually a global clock buffer in VirtexII which incoporates a smart mux to switch between 2 clock sources. More importantly, the BUFGMUX guarantees glitch-free switching between these 2 clocks, even though the select signal changes asynchronously. (参考译文:简单的方法是使用Xilinx VirtexII器件上的BUFGMUX资源. BUFGMUX实际上是VirtexII中的全局时钟缓冲, VirtexII将智能mux与2个时钟源之间的切换相结合. 更为重要的是, 即使选择信号更改不同步, BUFGMUX也能保证这两个时钟之间的无干扰切换. )
38. I am now going to design a gray coded 16 bits counter , any efficient way to implement it in VHDL description? (要设计一个灰色编码16位的计数器, 怎么以VHDL描述来实现它?)
答:You can just use megawizard(lpm_counter) in the software to generate the counter for you, select the output language with VHDL. That should be the efficient way to implement a counter, and you don't to make additional optimize.
Because the lpm function code is the best way to fit the structure of device, which is designed by altera factory specialist who is very familiar with our device structure. (参考译文:可以使用软件里的megawizard(lpm_counter)来生成计数器, 选择带有VHDL的输出语言. 这应该是实现计数器的有效方法, 而且不用进行额外的优化.