Enhanced features available in MAX 7000E and MAX 7000S devices – Six pin- or logic-driven output enable signals
41． 在FPGA中是以何种形式实现VHDL的变量类型的？
答：There is no definite answer to this. It depends on how you write your codes. A variable in vhdl may be synthesized into a physical net, or it may not exist at all in the resulting circuit. 文：没有明确的答案. 它取决于所编写的代码. Vhdl中的变量可能同步到物理网络中, 或者根本不可能存在于结果电路中. ）
答：Most synthesizers do preserve signal names to a certain extend, usually a string is concatenated to the end of the original name. So you can still correlate the names in many cases. For those strange net names like N***, they are signals generated by the synthesizer and may not have a counterpart in the original source code. （参考译文：大多数合成器是会以某种扩展名来保存信号名称, 这些扩展名通常是连接到最初的名称末尾的字符串. 使这些名称在很多情况下仍然相关. 至于那些像N***一样奇怪的网表名称, 是由合成器生成的信号, 而且可能不会在最初的源代码中有副本. ）
答：The timing information you get from the post-layout simulation is based on worst case parameter. So you usually have better results on silicon than in simulation. For robust designs, always consider the worst case. （参考译文：从时序仿真中获得的时序信息是基于最坏情况参数的. 因此, 通常在硅片上实际操作的结果要比仿真中的好. 对于可靠的设计而言, 始终都要考虑最坏的情况. ）
44． ISE4. 2和ISE4. 1相比有何改进?
答：Here's a brief list of new features in ISE4. 2i （以下是ISE4. 2i新特性的要点）
- Device support for VirtexII Pro and CoolRunnerII （设备支持VirtexII Pro和CoolRunnerII）
- Provides 2 new source types, BMM files and ELF files, for embedded VirtexII Pro PowerPC and Microblaze processor support. BMM file is the Block RAM Memory Map file that describes the organization of Block RAM memory. ELF file is the Executable and Linkable Format file contains the executable CPU code image to be stored in Block RAM as specified in the BMM file. （提供2个新的源类型：BMM文件和ELF文件, 以支持嵌入式VirtexII Pro PowerPC和Microblaze处理器. BMM文件是“块RAM内存图”文件, 它描述了块RAM内存的结构. ELF文件是“可执行和可链接格式”文件, 它包含存储在BMM文件中指定的块RAM的可执行CPU代码图. ）
- Improved PAD file for easier to import into a spreadsheet program for viewing, sorting and printing. （改进PAD文件, 以便导入到电子表格程序中, 供查看、存储和打印）
- iMPACT now incorporates the functionality of the PROM File Formatter and Xilinx System ACE software. （iMPACT与PROM文件格式程序和Xilinx系统ACE软件的功能相结合）
- XST enhancement for better language support and preservation of internal signal names. （XST增强了语言支持, 并能保存内部信号名称. ）
For more information regarding Xilinx ISE4. 2i, please visit our website www. xilinx. com （更多有关Xilinx ISE4. 2i的信息, 请访问网站www. xilinx. com）.
45． 经常看到gate这个词. 能够具体解释一下它的含义, 例举其用法以及如何避免问题？
答：Here're a couple of examples :（举例说明）
- Never use gated clock. By gated clock we mean the clock signal comes out from combinational logic. It is well known that any signal coming out of combinational logic is prone to glitch. The result is fatal if there is a glitch on your clock signal since it will cause false triggering of FFs. A common technique to avoid gated clock is to utilize the clock enable pin on the FF. （从不使用gated clock. 这个词表示时钟信号出自组合逻辑. 众所周知, 任何出自组合逻辑的信号都容易发生故障. 由于时钟信号上的故障将导致错误触发FF, 其结果是致命的. 避免gated clock常用的技巧是利用FF上的时钟使能引脚. ）
- Never design a circuit that relies on gate delay to function. It was a common practise in the past to introduce a delay in the design by inserting a series of logic gates. This is not a recommended style in modern high speed digital design since the delay changes as new devices coming out from more advance process technologies. Also, the amount of delay changes as temperature and voltage as well. So it is not a good design practice to have circuits which relies in gate delay to function. （绝不设计依赖gate delay工作的电路. 通过插入一系列逻辑门在设计中引入延迟, 这是以前常见的作法. 而在现代高速数字设计中, 建议不要使用这种作法, 因为延迟会随采用更先进的工艺技术所制造的新器件而改变. 而且, 延迟的总量也会随温度和电压而改变. 因此依赖gate delay而工作的电路不是很好的设计. ）
答：Thank you for your input. In fact there are a number of books available in the market on Xilinx FPGA and development tools. A good example is the title "XILINX 数字系统集成技术" by Professor 朱明程, published by Southeast University Press. We will work closely with local publishers to bring out more titles on Xilinx products. （市场上还是有几本Xilinx FPGA和开发工具的书. 比较好的有朱明程教授编的《XILINX 数字系统集成技术》, 东南大学出版社出版. Xilinx公司也将会与本地出版商密切合作, 推出更多针对Xilinx产品的书籍. ）
