MultiVolt I/O Interface（P2-60）
The Cyclone II architecture supports the MultiVolt I/O interface feature,
which allows Cyclone II devices in all packages to interface with systems
of different supply voltages. Cyclone II devices have one set of V
CC
pins
( VCCINT) that power the internal device logic array and input buffers that
use the LVPECL, LVDS, HSTL, or SSTL I/O standards. Cyclone II devices
also have four or eight sets of VCC pins (VCCIO ) that power the I/O
output drivers and input buffers that use the LVTTL, LVCMOS, or PCI
I/O standards.
The Cyclone II VCCINT pins must always be co nnected to a 1.2-V power
supply. If the V
CCINT
level is 1.2 V, then input pi ns are 1.5-V, 1.8-V, 2.5-V,
and 3.3-V tolerant. The VCCIO pins can be connected to either a 1.5-V,
1.8-V, 2.5-V, or 3.3-V power supply, depending on the output
requirements. The output levels are co mpatible with systems of the same
voltage as the power supply (i.e., when VCCIO pins are connected to a
1.5-V power supply, the output levels are compatible with 1.5-V systems).
When VCCIO pins are connected to a 3.3-V power supply, the output high
is 3.3-V and is compatible with 3.3-V systems.
Each I/O bank has its own VCCIO pins. A single de vice can support
1.5-V, 1.8-V, 2.5-V, and 3.3-V interfac es; each individual bank can support
a different standard with different I/O voltages. Each bank also has
dual-purpose VREF pins to support any one of the voltage-referenced
standards (e.g., SSTL-2) independently. If an I/O bank does not use
voltage-referenced standards, the VREF pins are available as user I/O
pins.
Each I/O bank can support multiple standards with the same VCCIO for
input and output pins. For example, when V
CCIOis 3.3-V, a bank can support LVTTL, LVCMOS, and 3.3-V PCI for inputs and outputs.
Voltage-referenced standards can be supported in an I/O bank using any
number of single-ended or differential standards as long as they use the
same VREF and a compatible VCCIO value.
The Cyclone II architecture supports the MultiVolt I/O interface feature,
which allows Cyclone II devices in all packages to interface with systems
of different supply voltages. Cyclone II devices have one set of VCC pins
( VCCINT) that power the internal device logic array and input buffers that
use the LVPECL, LVDS, HSTL, or SSTL I/O standards. Cyclone II devices
also have four or eight sets of VCC pins (VCCIO ) that power the I/O
output drivers and input buffers that use the LVTTL, LVCMOS, or PCI
I/O standards.
The Cyclone II VCCINT pins must always be co nnected to a 1.2-V power supply. If the V
CCINT level is 1.2 V, then input pi ns are 1.5-V, 1.8-V, 2.5-V,
and 3.3-V tolerant. The VCCIO pins can be connected to either a 1.5-V,
1.8-V, 2.5-V, or 3.3-V power supply, depending on the output
requirements. The output levels are co mpatible with systems of the same
voltage as the power supply (i.e., when VCCIO pins are connected to a
1.5-V power supply, the output levels are compatible with 1.5-V systems).
When VCCIO pins are connected to a 3.3-V power supply, the output high
is 3.3-V and is compatible with 3.3-V systems.
