CLKIN使用GCLK脚，基本无使用问题。
但由于板上的布线及管脚限制，第一板使用了LHCLK脚，使用ISE10.1相关附属工具 Architecture Wizard产生
DCM模块，在对管脚约束后，CLKIN使用LHCLK脚（XS3C100E-TQ144，P88 脚），用ISE综合后PALCE&ROUTE产生如
下错误(ISE版本：10.1 nt):
ERRORlace:1012 - A clock IOB / DCM component pair have been found that are not placed at an
optimal clock IOB / DCM
site pair. The clock component <DCM_SP_INST> is placed at site <DCM_X0Y0>. The clock IO/DCM
site can be paired if
they are placed/locked in the same quadrant. The IO component <CLKIN_IN> is placed at site
<88>. This will not
allow the use of the fast path between the IO and the Clock buffer. If this sub optimal
condition is acceptable for
this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this
message to a WARNING
and allow your design to continue. However, the use of this override is highly discouraged as
it may lead to very
poor timing results. It is recommended that this error condition be corrected in the design. A
list of all the
COMP.PINs used in this clock placement rule is listed below. These examples can be used
directly in the .ucf file to
override this clock rule.
< NET "CLKIN_IN" CLOCK_DEDICATED_ROUTE = FALSE; >
< PIN "DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; >
错误原因：由于非GCLK脚不具有BUFG，在 PALCE&ROUTE由于为找到IBUFG而出错。
解决方法：
不同的ISE版本对这个问题的error报告建议的解决 方式是不一样的，如7.1的error建议是修改环境变量，
“可以设置一个环境变量 XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING，将其设置为1，这样可以将error变为warning
”；10.1是 建议使用CLOCK_DEDICATED_ROUTE，语法是：NET "signal_name" CLOCK_DEDICATED_ROUTE = FALSE
。
另有网友提出：“最好的办法是将每个dcm的buf输出变为两个以下，就不会出现这种错误了”。
以 上几种方法都未尝试，不知是否可行。
最后选则在Architecture Wizard生成的DCM模块中，将使用IBUFG的用BUFG替换，结果可行。
IBUFG { .I( input_clk )
.O( output_clk )
}
↓
BUFG { .I( input_clk )
.O( output_clk )
}
但需要注意的是，时序不能太紧张，否则工程会有时满足时序，有时不满足。
实际测 试使用XS3C100E-4TQ144，P88脚输入12MHz，P14脚输出CLKFX_OUT，输出设置50MHz，用示波器测得结果
正确。
关 于CLK0的反馈问题，需要进一步实验、探讨。
lace:1012 - A clock IOB / DCM component pair have been found that are not placed at an 
88>. This will not