标题:
基于FPGA的数字时钟数码管显示(2)
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作者:
yuyang911220
时间:
2015-12-23 16:54
标题:
基于FPGA的数字时钟数码管显示(2)
//模式选择
//state = 2'b00 时钟计时
//state = 2'b01 小时校准
//state = 2'b10 分钟校准
//state = 2'b11 秒校准
always @(negedge mode or negedge clr)
if(!clr)
state = 2'b00;
else if(!mode)
begin
case(state)
2'b00: state = 2'b01;
2'b01: state = 2'b10;
2'b10: state = 2'b11;
2'b11: state = 2'b00;
endcase
end
reg[25: 0] clk_cnt;
reg set_r;
always @(posedge clk or negedge clr)
if(!clr)
begin
sec = 8'd0;
min = 8'd0;
hour = 8'd0;
clk_cnt = 0;
set_r = 1'b0;
end
else
begin
case(state)
2'b00:
//24小时计数
if(clk_cnt == 26'd50000000)
//对50M时钟进行分频得1Hz的时钟
begin
clk_cnt = 25'd0;
if(sec == 8'd59)
begin
sec = 8'd0;
if(min == 8'd59)
//时钟计数
begin
min = 8'd0;
if(hour == 8'd23)
hour = 8'd0;
else
hour = hour + 1'b1;
end
else
min = min + 1'b1;
end
else
sec = sec + 1'b1;
end
else
clk_cnt = clk_cnt + 1'b1;
2'b01:
//小时校准
if(!set)
begin
if(set_r == 1'b0)
begin
set_r =1'b1;
if(hour == 8'd23)
hour = 8'd0;
else
hour = hour + 1'b1;
end
end
else
set_r = 1'b0;
2'b10:
//分钟校准
if(!set)
begin
if(set_r == 1'b0)
begin
set_r = 1'b1;
if(min == 8'd59)
min = 8'd0;
else
min = min + 1'b1;
end
end
else
set_r = 1'b0;
2'b11:
//秒校准
if(!set)
begin
if(set_r == 1'b0)
begin
set_r =1'b1;
if(sec == 8'd59)
sec = 8'd0;
else
sec = sec + 1'b1;
end
end
else
set_r = 1'b0;
endcase
end
endmodule
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