英文原文:
Swapping bits improves performance of FPGA-PWM counter
A simple change to the specification of an FPGA counter lowers the ripple of a PWM counter functioning as a DAC.
Stefaan Vanheesbeke, Ledegem, Belgium; Edited by Charles H Small and Fran Granville -- EDN, 9/13/2007
When you need some analog outputs and you have an FPGA in your system, you probably choose to use a PWM module and a simple lowpass filter such as those in Figure 1. The output of the FPGA is typically a waveform with a fixed-frequency, variable-duty cycle, which a counter and a digital comparator generate (Listing 1).
Suppose that Enable is high, the counter counts up every clock cycle, and the frequency of the PWM output is the clock frequency divided by 2 count bits. You can use Enable to lower the output frequency by connecting it to a prescaler. Because the output frequency is fixed, the filter is easy to calculate, because you know that the worst-case ripple happens at a duty cycle of 50%. The combination of the desired maximum ripple and settling time determines the filter type and RC (resistance/capacitance) values.