library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity check is
port(
clk_8k: IN std_logic;
state_t:OUT std_logic
);
end;
architecture a of check is
begin
process(clk_8k)
begin
if falling_edge(clk_8k) then
state_t <= '1';
else
state_t <= '0';
end if;
end process;
end a;
出现了报错：@E: CL123 :"E:\test2\check.vhd":17:1:17:2|Logic for state_t_3 does not match a standard flip-flop
这个是什么原因啊？如何修改呢？
