library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

--synopsys translate_on
entity mcjc is
    Port ( a_in : in  STD_LOGIC;
           q_out : out  STD_LOGIC);
end mcjc;

architecture Behavioral of mcjc is
signal b,c,d,e:STD_LOGIC;

begin
process(a_in)
begin
b<=a_in;
c<=b;
d<=c;
e<=d;
q_out<=a_in and b and c and d and e;

end process;

end Behavioral;

我的程序编译没什么问题，可是仿真出来，没有输出，不知道是怎么回事，大家帮忙看一下哪出了问题？谢谢1