library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--************************************
ENTITY VHDl2 is
port( A: in STD_LOGIC;
B: in STD_LOGIC;
C: in STD_LOGIC;
Z: out STD_LOGIC
);
END VHDL2;
--************************************
ARCHITECTURE VHDL2_E OF VHDL2 is
SIGNAL D,E : STD_LOGIC;
component INV port(I,H: in STD_LOGIC; O: out STD_LOGIC);END component;
component AND2 port(I0,H0: in STD_LOGIC; O: out STD_LOGIC);END component;
component OR2 port(I1,H1: in STD_LOGIC; O: out STD_LOGIC);END component;
BEGIN
U1: AND2 port map (A,B,D);
U2: INV port map(B,E);
U3: or2 port map(D,E,Z);
