1。我在ISE中启动modelsim时出现了下面的错误
Loading work.tb_ic1_func
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# Loading work.fifoctlr_ic_v2
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) fifoctlr_ic_v2.v(126): Instantiation of 'BUFGP' failed. The design unit was not found.
是什么原因？
“点到仿真模式，在source里面选中你建立工程选择的芯片，然后看Processes，点开，有个compile HDL simulation library，运行一下就OK了”
2.ISE用modelsim仿真提示：# ** Error: (vish-4014) No objects found matching '*'.结果仿真时老是报错：
# ** Error: (vish-4014) No objects found matching '*'.
# Error in macro ./test_top_tb.fdo line 10
# (vish-4014) No objects found matching '*'.
# while executing
# "add wave *"
解决办法，改modelsim.ini文件中的一个参数：VoptFlow = 03.当对IP核修改后，用Modelsim仿真显示：No entity is bound for inst 或 CE is not in the entity。（CE是改动后添加的一个管脚），从而仿真无结果。
解决办法：首先选中该IP核的.xco文件点击右键->属性 将属性改为 "Synthesis/Imp + Simulation."
然后将其对应的.v或.vhd文件的属性也改为 "Synthesis/Imp + Simulation."
4.启动modelsim后，没有出错，但是有warning：(vsim-3009) [TSCALE] - Module 'ODDR' does not have a `timescale directive in effect, but previous modules do.输入信号均正确，调用的IP core或原语的输出为高阻态。
解决办法：modelsim中调用该IP core或原语的库不匹配，在xilinx中找到其所在的库unisims，并重新编译至modelsim的UNISIMS_VER库中。问题可得到解决。
