always@(posedge clk)
begin
if(!rst) begin dout_1 <= 32'h00000000;en_1 <= 0; end
else if(en) begin dout_1 <= data+32'h00000077;en_1 <= 1; end
else en_1 <= 0;
end
always@(posedge clk)
begin
if(!rst) begin dout_2 <= 16'h0000;en_2 <= 0; end
else if(en_1) begin dout_2 <= dout_1[31:16];en_2 <= 1; end
else en_2 <= 0;
end
always@(posedge clk)
begin
if(!rst) begin dout_3 <= 16'h0000;en_3 <= 0; end
else if(en_2) begin dout_3 <= dout_2-num;en_3 <= 1; end
else en_3 <= 0;
end
always@(posedge clk)
begin
if(!rst) begin dout <= 8'h00;en_out <= 0; end
else if(en_3) begin dout <= dout_3[7:0];en_out <= 1; end
else en_out <= 0;
end