1 | struct net_device * __init oeth_init(int unit); |
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 | typedef struct _oeth_regs { uint moder; /* Mode Register */ uint int_src; /* Interrupt Source Register */ uint int_mask; /* Interrupt Mask Register */ uint ipgt; /* Back to Bak Inter Packet Gap Register */ uint ipgr1; /* Non Back to Back Inter Packet Gap Register 1 */ uint ipgr2; /* Non Back to Back Inter Packet Gap Register 2 */ uint packet_len; /* Packet Length Register (min. and max.) */ uint collconf; /* Collision and Retry Configuration Register */ uint tx_bd_num; /* Transmit Buffer Descriptor Number Register */ uint ctrlmoder; /* Control Module Mode Register */ uint miimoder; /* MII Mode Register */ uint miicommand; /* MII Command Register */ uint miiaddress; /* MII Address Register */ uint miitx_data; /* MII Transmit Data Register */ uint miirx_data; /* MII Receive Data Register */ uint miistatus; /* MII Status Register */ uint mac_addr0; /* MAC Individual Address Register 0 */ uint mac_addr1; /* MAC Individual Address Register 1 */ uint hash_addr0; /* Hash Register 0 */ uint hash_addr1; /* Hash Register 1 */ } oeth_regs; |
1 2 3 4 5 6 7 8 9 10 11 12 | dev->open = oeth_open; dev->hard_start_xmit = oeth_start_xmit; dev->stop = oeth_close; dev->get_stats = oeth_get_stats; dev->set_multicast_list = oeth_set_multicast_list; dev->set_mac_address = oeth_set_mac_add; bmcr_val = eth_mdread(dev, PHY_ADDRESS, MII_BMCR); dev->do_ioctl = mii_ioctl; cep->mii.dev = dev; cep->mii.mdio_read = eth_mdread; cep->mii.mdio_write = eth_mdwrite; |
1 2 3 4 5 6 7 | /*Install eth interrupt handler*/ request_irq(MACIRQ_NUM, oeth_interrupt, 0, "eth", (void *)dev); /*Enable receiver and transmitter */ regs->moder |= OETH_MODER_RXEN | OETH_MODER_TXEN; /*set tasklet for receiver and transmitter*/ tasklet_init(&cep->oeth_rx_tasklet, oeth_rx, (unsigned long)dev); tasklet_init(&cep->oeth_tx_tasklet, oeth_tx, (unsigned long)dev); |
1 2 3 4 5 6 | /* Handle receive event in its own function.*/ if (int_events & (OETH_INT_RXF | OETH_INT_RXE | OETH_INT_BUSY)) tasklet_schedule(&cep->oeth_rx_tasklet); /* Handle transmit event in its own function. */ if (int_events & (OETH_INT_TXB | OETH_INT_TXE)) tasklet_schedule(&cep->oeth_tx_tasklet); |
1 2 3 4 5 | cep->mii.mdio_read = eth_mdread;//读PHY寄存器 cep->mii.mdio_write = eth_mdwrite;//写PHY寄存器 cep->mii.phy_id_mask = 0x1f; cep->mii.reg_num_mask = 0x1f; cep->mii.phy_id = PHY_ADDRESS; |
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