function mask_5(data1,data2,data3,data4,data5,data6,data7,data8,data9,data10,data11,data12,data13,data14,data15,data16,data17,data18,data19,data20,data21,data22,data23,data24,data25 : std_logic_vector(7 downto 0)) ------------（提示错误为：Error: VHDL error at filter.vhd(75): formal port or parameter "data23" must have actual or default value）
         return integer is
         variable d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15,d16,d17,d18,d19,d20,d21,d22,d23,d24,d25 : integer ;
         variable sum_5 : integer ;
begin
        d1 := CONV_INTEGER(data1);
        d2 := CONV_INTEGER(data2);
        d3 := CONV_INTEGER(data3);
        d4 := CONV_INTEGER(data4);
        d5 := CONV_INTEGER(data5);
        d6 := CONV_INTEGER(data6);
        d7 := CONV_INTEGER(data7);
        d8 := CONV_INTEGER(data8);
        d9 := CONV_INTEGER(data9);
        d10 := CONV_INTEGER(data10);
        d11 := CONV_INTEGER(data11);
        d12 := CONV_INTEGER(data12);
        d13 := CONV_INTEGER(data13);
        d14 := CONV_INTEGER(data14);
        d15 := CONV_INTEGER(data15);
        d16 := CONV_INTEGER(data16);
        d17 := CONV_INTEGER(data17);
        d18 := CONV_INTEGER(data18);
        d19 := CONV_INTEGER(data19);
        d20 := CONV_INTEGER(data20);
        d21 := CONV_INTEGER(data21);
        d22 := CONV_INTEGER(data22);
        d23 := CONV_INTEGER(data23);
        d24 := CONV_INTEGER(data24);
        d25 := CONV_INTEGER(data25);
        sum_5 := d1+d2+d3+d4+d5+d6+d7+d8+d9+d10+d11+d12+d13+d14+d15+d16+d17+d18+d19+d20+d21+d22+d23+d24+d25 ;
        return sum_5;
end mask_5;

下面是函数调用时的错误：
process (reset_n, iCLK)
 begin
  if (reset_n = '0') then
   mask_reg <= (others=>'0');
  elsif (iCLK'event and iCLK = '1') then
      if (enable = '1') then
     mask_reg <= din;
                        if (mask_reg(103 downto 96) = "11111111")then
                           if ( mask_5(mask_reg(7 downto 0),mask_reg(15 downto 8),mask_reg(23 downto 16),mask_reg(31 downto 24),mask_reg(39 downto 32),mask_reg(47 downto 40),mask_reg(55 downto 48),mask_reg(63 downto 56),mask_reg(71 downto 64),mask_reg(79 downto 72),mask_reg(87 downto 80),mask_reg(95 downto 88),mask_reg(103 downto 96),mask_reg(111 downto 104),mask_reg(119 downto 112),mask_reg(127 downto 120),mask_reg(135 downto 128),mask_reg(143 downto 136),mask_reg(151 downto 144),mask_reg(159 downto 152),mask_reg(167 downto 160),mask_reg(175 downto 168),mask_reg(183 downto 17),mask_reg(191 downto 184),mask_reg(199 downto 192))<5*255)then---------(错误提示：Error: VHDL expression error at filter.vhd(383): expression has 167 elements, but must have 8 elements)
                             oDATA <= (others=>'0');
                           end if;
                        end if;
                      end if;
      end if;
 end process;