library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity RAM2RW256xM is
    generic(WORD_WIDTH     :integer := 32 );
    port(
        clk            :in std_logic;
        pass           :in std_logic_vector(3 downto 0); -- unused except in altera
        wea            :in std_logic;
        web            :in std_logic;
        addra          :in std_logic_vector(7 downto 0);
        addrb          :in std_logic_vector(7 downto 0);
        dataina        :in std_logic_vector(WORD_WIDTH-1 downto 0);
        datainb        :in std_logic_vector(WORD_WIDTH-1 downto 0);
        dataouta       ut std_logic_vector(WORD_WIDTH-1 downto 0);
        dataoutb       ut std_logic_vector(WORD_WIDTH-1 downto 0));
end RAM2RW256xM;

architecture behavior of RAM2RW256xM is

    type ram_type is array(0 to 255) of
         Std_Logic_Vector(WORD_WIDTH-1 downto 0);
    signal ram:ram_type;
       
begin
  
    process
    begin
       wait until clk'event and clk='1';
       dataouta <= ram(CONV_INTEGER(addra));
       dataoutb <= ram(CONV_INTEGER(addrb));
    end process;

    process
    begin
       wait until clk'event and clk='1';
       if (wea = '1') then
          ram(CONV_INTEGER(addra)) <= dataina;
       end if;
       if (web = '1') then
          ram(CONV_INTEGER(addrb)) <= datainb;
       end if;
    end process;

end behavior;

上面的dual ports ram 为什么在quartus 软件下编译时间超长,而中间不提示错误呢?

dual ports ram 在quartus中不是有ip可以生成吗？

使用自动生成的方式比较好。

时间长就是用LE产生去了

建议你到Altera网站下载个例子，按照它的写法才能正常综合出用M4K的实现