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标题: [讨论]请问在Q2中怎么新建testbench [打印本页]

作者: flyfpga    时间: 2007-11-30 21:26     标题: [讨论]请问在Q2中怎么新建testbench

请问在Q2中怎么新建testbench?我用的是Q2,请问我要用testbench验证该怎么办?


作者: caopengly    时间: 2007-12-1 00:00

quartus2 中不能使用testbench来作为测试工具。

你可以使用modelsim来测试程序,modelsim支持testbench。


作者: flyfpga    时间: 2007-12-7 21:48

testbench也是.vhd格式吗?或者说怎么新建testbench文件啊?


作者: caopengly    时间: 2007-12-7 22:27

testbench也是.vhd格式吗?或者说怎么新建testbench文件啊?

是的,就是,这个和一般的vhdl有一点区别,如

VHDL 示例
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench is
end entity testbench;
architecture test_reg of testbench is
component shift_reg is
port ( clock : in std_logic;
reset : in std_logic;
load : in std_logic;
sel : in std_logic_vector(1 downto 0);
data : in std_logic_vector(4 downto 0);
shiftreg : out std_logic_vector(4 downto 0));
end component;
signal clock, reset, load: std_logic;
signal shiftreg, data: std_logic_vector(4 downto 0);
signal sel: std_logic_vector(1 downto 0);
constant ClockPeriod : TIME := 50 ns;
begin
UUT : shift_reg port map (clock => clock, reset => reset,
load => load, data => data,
shiftreg => shiftreg);
process begin
clock <= not clock after (ClockPeriod / 2);
end process;
process begin
reset <= ’1’;
data <= "00000";
load <= ’0’;
set <= "00";
wait for 200 ns;
reset <= ’0’;
load <= ’1’;
wait for 200 ns;
data <= "00001";
wait for 100 ns;
sel <= "01";
load <= ’0’;
wait for 200 ns;
sel <= "10";
wait for 1000 ns;
end process;
end architecture test_reg;






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