Error: Specified DDIO registers are not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:7:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:6:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:0:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:4:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:1:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:3:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:2:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|output_cell_L[0]" is not part of a legal DDIO circuit
	Error: Register "SCPU:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:\g_dq_io:5:dq_io|ddio_bidir_c0l:auto_generated|output_cell_H[0]" is not part of a legal DDIO circuit
Error: Can't fit design in device
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
	Info: Pin SDR_CKE has VCC driving its datain port
Info: Following groups of pins have the same output enable
	Info: Following pins have the same output enable: group 1
		Info: Type bidirectional pin ddr_dqs[0] uses the SSTL-2 Class I I/O standard
		Info: Type bidirectional pin ddr_dqs[1] uses the SSTL-2 Class I I/O standard
	Info: Following pins have the same output enable: SCPU:inst|tristate_bridge_avalon_slave_arbitrator:the_tristate_bridge_avalon_slave|d1_in_a_write_cycle
		Info: Type bidirectional pin FLASH_DATA[3] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin FLASH_DATA[4] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin FLASH_DATA[0] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin FLASH_DATA[5] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin FLASH_DATA[1] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin FLASH_DATA[6] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin FLASH_DATA[2] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin FLASH_DATA[7] uses the 3.3-V LVTTL I/O standard
	Info: Following pins have the same output enable: SCPU:inst|sdram:the_sdram|oe
		Info: Type bidirectional pin SDR_DATA[27] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[19] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[11] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[3] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[28] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[24] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[20] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[16] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[12] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[8] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[4] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[0] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[29] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[25] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[21] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[17] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[13] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[9] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[5] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[1] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[30] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[26] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[22] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[18] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[14] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[10] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[6] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[2] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[31] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[23] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[15] uses the 3.3-V LVTTL I/O standard
		Info: Type bidirectional pin SDR_DATA[7] uses the 3.3-V LVTTL I/O standard
Error: Quartus II Fitter was unsuccessful. 34 errors, 4 warnings
	Info: Allocated 217 megabytes of memory during processing
	Error: Processing ended: Tue Dec 04 16:06:05 2007
	Error: Elapsed time: 00:00:15