LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY test IS
PORT
(
clk : IN STD_LOGIC;
q : buffer STD_LOGIC );
END test;
ARCHITECTURE a OF test IS
BEGIN
PROCESS (clk)
begin
if(clk'event and clk='1')then
q<=not q;
end if;
end process;
END a;
其中clk为输入信号，Q为分频后信号。作者: sccgjchn@hotmai 时间: 2004-3-5 09:46
