Board logo

标题: [分享]verilog语言16阶FIR [打印本页]

作者: sgoldfishl    时间: 2007-12-19 10:12     标题: [分享]verilog语言16阶FIR

module fir(clk,x,y);

input[7:0] x;

input clk;

output[15:0] y;

reg[15:0] y;

reg[7:0] tap0,tap1,tap2,tap3,tap4,tap5,tap6,tap7,tap8,tap9,tap10,tap11,tap12,tap13,tap14,tap15;

reg[7:0] t0,t1,t2,t3,t4,t5,t6,t7;

reg[15:0] sum;

always@(posedge clk)

begin

t0<=tap0+tap15;

t1<=tap1+tap14;

t2<=tap2+tap13;

t3<=tap3+tap12;

t4<=tap4+tap11;

t5<=tap5+tap10;

t6<=tap6+tap9;

t7<=tap7+tap8; //利用对称性

sum<={t0[7],t0[7:1]}-{t0[7],t0[7],t0[7],t0[7],t0[7],t0[7:5]} -t1-{t1[7],t1[7:1]}-{t1[7],t1[7],t1[7],t1[7:3]}

+(t2<<2)+t2+{t2[7],t2[7],t2[7:2]}+{t2[7],t2[7],t2[7],t2[7],t2[7:4]}

+{t2[7],t2[7],t2[7],t2[7],t2[7],t2[7:5]}

-{t3<<3}-(t3<<2)+t3-{t3[7],t3[7],t3[7:2]}

+(t4<<4)+t4-{t4[7],t4[7],t4[7],t4[7:3]}

-{t5<<7}+{(t5<<2)<<2}+(t5<<2)-{t5[7],t5[7:1]}

-{t5[7],t5[7],t5[7:2]}-{t5[7],t5[7],t5[7],t5[7],t5[7:4]}

+(t6<<7)+(t6<<3)-(t7<<7)-(t7<<6);

tap15<=tap14;tap14<=tap13;tap13<=tap12;tap12<=tap11;

tap11<=tap10;tap10<=tap9;tap9<=tap8;tap8<=tap7;

tap7<=tap6;tap6<=tap5;tap5<=tap4;tap4<=tap3;

tap3<=tap2;tap2<=tap1;tap1<=tap0;tap0<=x;

y<={sum[15],sum[15],sum[15],sum[15],sum[15],sum[15],sum[15],sum[15:7]};

end

endmodule


作者: songdong668    时间: 2007-12-21 18:14

xiexie
作者: pxjy    时间: 2009-4-1 22:05

谢谢




欢迎光临 电子技术论坛_中国专业的电子工程师学习交流社区-中电网技术论坛 (http://bbs.eccn.com/) Powered by Discuz! 7.0.0