verilog源程序
工具软件：ise5.2 modelsim5.7d
进行behavioral 仿真时出现以下错误：
Loading work.testbench
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# Loading work.system
# ** Warning: (vsim-3009) [TSCALE] - Module 'system' does not have a `timescale directive in effect, but previous modules do.
# Region: /testbench/UUT
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# Loading work.core
# ** Warning: (vsim-3009) [TSCALE] - Module 'core' does not have a `timescale directive in effect, but previous modules do.
# Region: /testbench/UUT/core0
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# Loading work.control_unit
# ** Warning: (vsim-3009) [TSCALE] - Module 'control_unit' does not have a `timescale directive in effect, but previous modules do.
# Region: /testbench/UUT/core0/control_unit0
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# Loading work.control_fsm
# ** Warning: (vsim-3009) [TSCALE] - Module 'control_fsm' does not have a `timescale directive in effect, but previous modules do.
# Region: /testbench/UUT/core0/control_unit0/control_fsm0
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# Loading work.control_mem
# ** Warning: (vsim-3009) [TSCALE] - Module 'control_mem' does not have a `timescale directive in effect, but previous modules do.
# Region: /testbench/UUT/core0/control_unit0/control_mem0
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# Loading work.alu
# ** Warning: (vsim-3009) [TSCALE] - Module 'alu' does not have a `timescale directive in effect, but previous modules do.
# Region: /testbench/UUT/core0/alu0
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
但在进行post-translate,post-map以及post-place&route时，错误就没了
请各位高手指教！！
