use work.bit_rtl_pkg.all;
--------------------------------------
-- Adder
--
--------------------------------------
entity bit_rtl_lib2 is
port (
in1 :in bit_vector(0 downto 0);
in2 :in bit_vector(0 downto 0);
cntl :in bit;
pout : out bit_vector(0 downto 0)
);
end bit_rtl_lib2;
architecture func of bit_rtl_lib2 is
begin
process(cntl)
begin
if (cntl = '1') then
pout <= in1+in2;
end if;
end process;
end func;
我是初学者~
请问大侠`为什么我在仿真时的波形和程序对不上？
也就是说当cntl=‘1’时pout不是in1+in2的值~作者: xxxydnw 时间: 2004-5-31 10:21
