library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity interface is port(clk:in std_logic; REFAut std_logic_vector(13 downto 0); REFBut std_logic_vector(13 downto 0)); end ; architecture dacc of interface is component datarom port(address: in std_logic_vector(3 downto 0); inclock: in std_logic; Q: out std_logic_vector(13 downto 0)); end component ; signal Q1: std_logic_vector(3 downto 0); begin process(clk) begin if clk'event and clk='1' then Q1<=Q1+1; end if ; end process; U1:datarom port map (address=>Q1,Q=>REFA,inclock=>clk); U2:datarom port map (address=>Q1+4,Q=>REFB,inclock=>clk); end;作者: caopengly 时间: 2008-1-16 15:52