我用VHDL编写的延时程序为何没有执行？是不是与设置有关？请知道的朋友告诉在下，谢谢！源程序如下：
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY delay IS
PORT(
RD:IN STD_LOGIC;
WR:IN STD_LOGIC;
DRD:OUT STD_LOGIC;
DWR:OUT STD_LOGIC
);
END delay;
ARCHITECTURE behave OF delay IS
SIGNAL READ:STD_LOGIC;
SIGNAL WRITE:STD_LOGIC;
BEGIN
PROCESS(RD,WR) -------RD和WR平时是高电平，变成低电平时有效
BEGIN
IF RD'EVENT AND RD='0' THEN
READ<=RD AFTER 5 nS;
END IF;
IF WR'EVENT AND WR='0' THEN
WRITE<=WR AFTER 5 nS;
END IF;
END PROCESS;
DRD<=READ;
DWR<=WRITE;
END behave;作者: green_pine 时间: 2004-5-8 14:50
