library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library lpm;
use lpm.lpm_componets.all;
entity ddsc is
generic(freq_width:integer:=32;
phase_width:integer:=12;
adder_width:integer:=32;
romad_width:integer:=10;
rom_d_width:integer:=10);
port(clk :in std_logic_vector(freq_width-1 downto 0);
freqin:in std_logic_vector(phase_width-1 downto 0);
phasein:in std_logic_vector(phase_width-1 downto 0);
ddsoutut std_logic_vector(rom_d_width-1 downto 0));
end entity ddsc;
architecture behave of ddsc is
signal acc:std_logic_vector(adder_width-1 downto 0);
signal phaseadd:std_logic_vector(phase_width-1 downto 0);
signal romaddr:std_logic_vector(romad_width-1 downto 0);
signal freqw:std_logic_vector(freq_width-1 downto 0);
signal phasew:std_logic_vector(phase_width-1 downto 0);
begin
process(clk)
begin
if(clk'event and clk ='1')then
freqw<=freqin;
phasew<=phasein;
acc<=acc+frqw;
end if;
end process;
phaseadd<=acc(adder_windth-1 downto adder_width-phase_width)+phasew;
romaddr<=phaseadd(phase_width-1 downto phase_width-romad_width);
i_rom: lpm_rom
generic map(lpmwidth=>rom_d_width,lpm_widthad=>romad_width,
lpm_address_control=>"unregistered",
lpm_outdata=>"sin_rom.mif")
port map(outclock=>clk,address=>romaddr,q=>ddsout);
end architecture behave;作者: green_pine 时间: 2004-5-8 14:24