原程序如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ch1 is
port(
pin48: in std_logic;
pin7: out std_logic);
end ch1;
architecture a of ch1 is
begin
pin7<=pin48;
end a;
错误如下：
Error:lin1:File d:\untitled2.vhd:vhdl design file "untitled2"must contain an entity of the same name
谢谢！
[em18]
