我的主程序如下:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity exp2_VHDL is
Port ( clk : in std_logic;
clr : in std_logic;
ckih : in std_logic;
s_l : in std_logic;
si : in std_logic;
pi : in std_logic_vector(7 downto 0);
mode:in std_logic_vector(2 downto 0);
qout : out std_logic_vector(7 downto 0));
end exp2_VHDL;

architecture Behavioral of exp2_VHDL is

component nand_3
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end component;

component xnor_2
Port ( a : in std_logic;
b : in std_logic;
y : out std_logic);
end component;

component deco138
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
g1 : in std_logic;
g2a : in std_logic;
g2b : in std_logic;
y : out std_logic_vector(7 downto 0));
end component;

component jkdff
Port ( pset : in std_logic;
clr : in std_logic;
clk : in std_logic;
j : in std_logic;
k : in std_logic;
qa : out std_logic;
qb : out std_logic);
end component;

component shift01
Port ( clr : in std_logic;
clk : in std_logic;
ckih : in std_logic;
s_l : in std_logic;
si : in std_logic;
pi : in std_logic_vector(7 downto 0);
q : out std_logic);
end component;

begin
process(clr,clk,ckih,s_l,si,pi,mode)
begin
case mode is
when "000"=> uut_nand_3:nand_3 port map(a=>pi(0),
b=>pi(1),
c=>pi(2),
y=>qout(0)
);

when "001"=> uut_xnor2: xnor_2 port map(a=>pi(0),
b=>pi(1),
y=>qout(0)
);

when "010"=> uut_deco138: deco138 port map(a=>pi(0),
b=>pi(1),
c=>pi(2),
g1=>pi(3),
g2a=>pi(4),
g2b=>pi(5),
y=>qout
);

when "011"=> uut_jkdff: jkdff port map(pset=>ckih,
clr=clr,
clk=>clk,
j=>pi(0),
k=>pi(1),
qa=>qout(0),
qb=>qout(1));

when "100"=> uut_shift01: shift01 port map(clr=>clr,
clk=>clk,
ckih=>ckih,
s_l=>s_l,
si=>si,
pi=>pi,
q=>qout
);
when others =>null;
end case;

end process;

end Behavioral;

错误信息:

Line 71. parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK
Line 77. parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK
Line 82. parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK
Line 91. parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK
Line 100. parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK