仿真可以的，但是下载后fpga控制adc0809的信号ale和start都不能产生，是状态机的问题还是其他什么问题。大家帮忙
　ADC0809 工作时序分析
ADC0809 的工作时序START是转换启动信号,高电平有效; ALE是3 位通道选择地址(ADDC、ADDB、ADDA) 信号的锁存信号. 当模拟量送至某一输入端,由3 位地址信号选择,而地址信号由ALE锁存; EOC是转换情况状态信号,当启动转换约100μs后,EOC产生一个负脉冲,以示转换结束;在EOC的上升沿后,若使输出使能信号OE为高电平,则控制
打开三态缓冲器,把转换好的8 位数据结果输送至数据总线.至此ADC0809的一次转换结束了.


状态机的程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adc0809 is
port(
reset : in std_logic;
clk : in std_logic;
eoc : in std_logic;
D : in std_logic_vector(7 downto 0);
lock : out std_logic;
ale : out std_logic;
start : out std_logic;
oe : out std_logic;
-- st : out integer range 7 downto 0;
adda : out std_logic;
addb : out std_logic;
addc : out std_logic;
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture func of adc0809 is
type state_type is (st0, st1, st2, st3, st4, st5, st6);
signal current_state,next_state : state_type:=st0;
signal lock1 : std_logic;
signal reg : std_logic_vector(7 downto 0);
begin
adda<='1';
lock<=lock1;
process (current_state, eoc)
begin
case current_state is
when st0=>
ale<='0';
start<='0';
oe<='0';
lock1<='0';
next_state<=st1;
when st1=>
ale<='1';
start<='0';
oe<='0';
lock1<='0';
next_state<=st2;
when st2=>
ale<='0';
start<='1';
oe<='0';
lock1<='0';
next_state<=st3;
when st3=>
ale<='0';
start<='0';
oe<='0';
lock1<='0';
if(eoc='0')then
next_state<=st4;
else
next_state<=st3;
end if;
when st4=>
ale<='0';
start<='0';
oe<='0';
lock1<='0';
if(eoc='1')then
next_state<=st5;
else
next_state<=st4;
end if;
when st5=>
ale<='0';
start<='0';
oe<='1';
lock1<='0';
next_state<=st6;
when st6=>
ale<='0';
start<='0';
oe<='1';
lock1<='1';
next_state<=st0;
when others=>
next_state<=st0;
end case;
end process;

process (clk,reset)
begin
if(reset='1')then
current_state<=st0;
elsif (clk'event and clk='1') then
current_state<=next_state;
end if;
end process;

process (lock1)
begin
if (lock1='1' and lock1'event) then
reg<=D;
end if;
end process;
data<=reg;
end func;