小弟用cyclone搞开发,环境:synplify综合工具,用modelsim进行后仿真出现一下错误恳请各位高手指正!!!
万谢!!!!
# vsim work.test
# Loading work.test
# Loading D:\Modeltech_5.8c\win32/../std.standard
# Loading D:\Modeltech_5.8c\win32/../ieee.std_logic_1164(body)
# Loading D:\Modeltech_5.8c\win32/../ieee.numeric_std(body)
# Loading D:\Program Files\synplicity\Synplify_751\lib\vhdl_sim\synplify.components
# Loading D:\Modeltech_5.8c\win32/../std.textio(body)
# Loading D:\Modeltech_5.8c\win32/../ieee.vital_timing(body)
# Loading D:\Modeltech_5.8c\win32/../ieee.vital_primitives(body)
# Loading D:\quartus\eda\sim_lib\cyclone.atom_pack(body)
# Loading D:\quartus\eda\sim_lib\cyclone.cyclone_components
# Loading D:\Modeltech_5.8c\win32/../verilog.vl_types(body)
# Loading work.command(beh)
# Loading D:\quartus\eda\sim_lib\cyclone.cyclone_lcell
# Loading D:\quartus\eda\sim_lib\cyclone.cyclone_asynch_lcell
# Loading D:\quartus\eda\sim_lib\cyclone.cyclone_lcell_register
# ** Error: (vsim-3056) Verilog port 'regcascin' must be connected to a VHDL signal or to OPEN when instantiated from VHDL.
# Region: /test/m/\II_state_6_# ** Error: (vsim-3056) Verilog port 'cin1' must be connected to a VHDL signal or to OPEN when instantiated from VHDL.
# Region: /test/m/\II_state_6_# ** Error: (vsim-3056) Verilog port 'cin0' must be connected to a VHDL signal or to OPEN when instantiated from VHDL.
# Region: /test/m/\II_state_6_# Loading D:\quartus\eda\sim_lib\cyclone.cyclone_io
# Loading D:\quartus\eda\sim_lib\cyclone.mux21
# Loading D:\quartus\eda\sim_lib\cyclone.dffe
# Loading D:\quartus\eda\sim_lib\cyclone.cyclone_asynch_io
# Error loading design
