标题:
我也发一个芒果机饮料机verilog hdl的程序和波形发生 和大家分享
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作者:
latin
时间:
2004-8-9 17:02
标题:
我也发一个芒果机饮料机verilog hdl的程序和波形发生 和大家分享
module boo (mian,clk, half,one,goods);
input [0:2]mian;
input clk;
output half,one,goods;
reg half,one,goods;
parameter t0=3'd0,t1=3'd1,t2=3'd2,t3=3'd3,t4=3'd4;
always @(posedge clk)
begin
case( mian)
t0:begin
half=1;
one=1;
goods=1;
end
t1:begin
one=1;
goods=1;
half=0;
end
t2:
begin
half=1;
goods=1;
one=0;
end
t3:
begin
one=1;
half=1;
goods=0;
end
t4:
begin
one=1;
goods=0;
half=0;
end
endcase
end
endmodule
module boo_test ;
reg [0:2]mian1;
reg clk1;
wire half1,one1,goods1;
boo b1(mian1,clk1,half1,one1,goods1);
initial
clk1=0;
always
begin
#25 clk1=~clk1;
end
always
begin
mian1= 3'd 4;
#55 mian1= 3'd 0;
#55 mian1= 3'd 1;
#55 mian1= 3'd 2;
#55 mian1= 3'd 3;
#55 mian1= 3'd 4;
end
endmodule
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