16-Bit Pulse Accumulator Control Register (PACTL)
0 |  AEN |  AMOD |  EDGE | CLK1 | CLK0 |  AOVI |  AI |
PAEN— Pulse Accumulator A System Enable
PAMOD— Pulse Accumulator Mode
PEDGE— Pulse Accumulator Edge Control
PAMOD | PEDGE | Pin Action |
0 | 0 | Falling edge |
0 | 1 | Rising edge |
1 | 0 | Div. by 64 clock enabled with pin high level |
1 | 1 | Div. by 64 clock enabled with pin low level |
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64 since the ¸64 clock is generated by the timer prescaler.
CLK1 | CLK0 | Clock Source |
0 | 0 | Use timer prescaler clock as timer counter clock |
0 | 1 | Use PACLK as input to timer counter clock |
1 | 0 | Use PACLK/256 as timer counter clock frequency |
1 | 1 | Use PACLK/65536 as timer counter clock frequency |
请问:PACLK时钟与Div. by 64 clock 时钟是什么关系,还有它们与总线时钟又是什么关系??
Div. by 64 clock的时钟,是不是总线时钟除64??
先谢谢了!!
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