//Set clock divider(plus setting check)
if(!FCLKDIV_FDIVLD) {
FCLKDIV = 0x4F; /* Set up Clock Divider Register */
}
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//clear the running environment
FSTAT_PVIOL = 1; //set 1 to clear the flag,writing 0 has no effect on PVIOL. while PVIOL is set, it's not possilbe for the flash unit control SM to run on.
FSTAT_ACCERR = 1; // the same reason as above
//flush the flash sector first
//Write dummy data to flash unit buffer
ptr = hard_addr ;
*ptr = 0x11;//send dummy data to flash write buffer
//deliver the command to FCMD
FCMD = 0x40;
//lauch the instruction execution
FSTAT_CBEIF = 1;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//write data to corresponding memory
//clear the running environment
for(loop_counter=0;loop_counter<11;loop_counter++) {
FSTAT_PVIOL = 1; //set 1 to clear the flag,writing 0 has no effect on PVIOL. while PVIOL is set, it's not possilbe for the flash unit control SM to run on.
FSTAT_ACCERR = 1; // the same reason as above
//Write dummy data to flash unit buffer
*(WORD* )ptr = (WORD) data_buffer[loop_counter*2+1];//send dummy data to flash write buffer
ptr++;
//deliver the command to FCMD
FCMD = 0x20;
//lauch the instruction execution
FSTAT_CBEIF = 1;
//FSTAT checking
if(FSTAT_PVIOL ) break;
if(FSTAT_ACCERR ) break;
//wait until execution complete
while(FSTAT_CCIF ==0 ) ; //idle loop waiting earasure op. completed
}
__EI();