library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--**************************
entity fifo is
generic( d : integer:=8;
w : integer:=4
);
port(
clk : in std_logic;
reset : in std_logic;
wr : in std_logic;
rd : in std_logic;
din : in std_logic_vector(w-1 downto 0);
dout : out std_logic_vector(w-1 downto 0);
full : out std_logic;
empty : out std_logic
);
end fifo;
--******************************************
architecture behav of fifo is
type memory is array(0 to d-1) of std_logic_vector(w-1 downto 0);
signal RAM:memory;
signal wp,rp: integer range 0 to d-1;
signal in_full,in_empty: std_logic;
begin
full <=in_full;
empty<=in_empty;
dout <=RAM(rp);
process(clk)--FIFO的数据压入操作
begin
if(clk'event and clk='1')then
if(wr='0'and in_full='0')then
RAM(wp)<=din;
end if;
end if;
end process;
process(clk,reset)--描述写数据地址指示器WP的数值修改
begin
if(reset='1')then
wp<=0;
elsif(clk'event and clk='1')then
if(wr='0' and in_full='0')then
if(wp=w-1)then
wp<=0;
else
wp<=wp+1;
end if;
end if;
end if;
end process;
process(clk,reset)--描述读数据地址指示器rp的数值修改
begin
if(reset='1')then
rp<=w-1;
elsif(clk'event and clk='1')then
if(rd='0' and in_empty='0')then
if(rp=w-1)then
rp<=0;
else
rp<=rp+1;
end if;
end if;
end if;
end process;
process(clk,reset)--描述空标志的产生
begin
if(reset='1')then
in_empty<='1';
elsif(clk'event and clk='1')then
if(rp=wp-2 or(rp=w-1 and wp=1)or(rp=wp-2 and wp=0)) and(rd='0' and wr='1')then
in_empty<='1';
elsif(in_empty='1' and wr='0')then
in_empty<='0';
end if;
end if;
end process;
process(clk,reset)--描述满标志产生
begin
if(reset='1')then
in_full<='0';
elsif(clk'event and clk='1')then
if(rp=wp and wr='0' and rd='1')then
in_full<='1';
elsif(in_full='1' and rd='0')then
in_full<='0';
end if;
end if;
end process;
end behav;作者: bocolia 时间: 2004-12-15 16:27
