我感觉 for i in 0 to 15 loop
wait until rising_edge(clk);
循环和等待嵌套有问题，你看看先！作者: wuxianglin 时间: 2005-2-22 10:24 标题: 新手求助：各位大侠帮我看看程序
Library IEEE;
use IEEE.std_logic_1164.all;
package coeffs is
type coef_arr is array (0 to 16) of signed (8 downto 0);
constant coefs: coef_arr:=(
"000000001", "000000001", "000000000", "000000001",
"111111111", "111111110", "000000011", "000000010",
"111111110", "000000010", "000000000", "111111110",
"111111111", "000000001", "000000001", "111111110",
"111111101");
end coeffs;
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.coeffs.all;
entity fir is
port(clk,reset: in std_logic;
sample: in signed(7 downto 0);
result: out signed ( 16 downto 0));
end fir;
architecture beh of fir is
begin
process
type shift_arr is array (16 downto 0) of signed (7 downto 0);
variable tmp,old:signed(7 downto 0);
variable pro:signed (16 downto 0);
variable acc:signed (16 downto 0);
variable shift:shift_arr;
begin
for i in 0 to 15 loop --zero out the shift register
shift(i):=(others=>'0');
end loop;
result<=(others=>'0');
acc:=(others=>'0');
tmp:=sample;
for i in 0 to 15 loop
wait until rising_edge(clk);
shift(0):=tmp;
old:=shift(i);
pro:=shift(0) * coefs(i);
acc:=acc + pro;
shift(i+1):=shift(i);
end loop;
result<=acc;
end process;
end beh;
在循环语句运行中，老是出错，请各位大侠指点，谢谢！！
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.0 Build 190 1/28/2004 SJ Web Edition
Info: Processing started: Fri Jan 14 09:32:30 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Fir -c Fir
Info: Found 1 design units and 0 entities in source file coeffs.vhd
Info: Found design unit 1: coeffs
Info: Found 2 design units and 1 entities in source file Fir.vhd
Info: Found design unit 1: fir-beh
Info: Found entity 1: fir
Error: VHDL Process Statement error at Fir.vhd(27): Process Statement must contain only one Wait Statement
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
Error: Processing ended: Fri Jan 14 09:32:31 2005
Error: Elapsed time: 00:00:00
Error: Quartus II Full Compilation was unsuccessful. 1 error, 0 warnings
但是我要在循环语句内等到clk到来时付值，不知道怎么更改。
[此贴子已经被作者于2005-1-15 10:39:56编辑过]
作者: wuxianglin 时间: 2005-2-22 10:24
但是我用
if clk'event and clk='1'
代替 wait until 效果是一样的啊
