标题:
求助:verilog测试xilinxIP里的除法器无法仿真
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作者:
ksfblc
时间:
2008-5-28 21:00
标题:
求助:verilog测试xilinxIP里的除法器无法仿真
错误提示如下:
# ** Error: (vsim-3033) Divider29_6_29.v(94): Instantiation of 'DIV_GEN_V1_0' failed. The design unit was not found.
# Region: /b_v/uut
# Searched libraries:
# E:\Xilinx91i\verilog\mti_se\XilinxCoreLib_ver
# E:\Xilinx91i\verilog\mti_se\unisims_ver
# work
# Loading work.glbl
# Error loading design
请客大家应该怎么处理啊?
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