不知道这句程序是否正确：
entity full_adder is
port(sut std_logic;
Co: in std_logic
);
end full_adder;
architecture behave of full_adder is
begin
process(s)
vaiable ai:integer;
begin
si :=1;
case si is
when 0 => s=>'0';Co =>'0';
when 1 => s=>'0';Co =>'1';
when others=>s=>'x';Co=>'0';
end case;
end process
end behave;
ut std_logic;