entity adder is
generic(n : integer :=8);
port ( a : in std_logic_vector((n-1) downto 0);
b : in std_logic_vector((n-1) downto 0);
c : out std_logic_vector((n-1) downto 0));
end adder;
这样的实体在testbench中怎么写map？我这样写不对：

library ieee;

use ieee.std_logic_1164.all;

entity test_adder is

end test_adder ;

architecture test _bench of test_adder is

component adder
generic(n : integer :=8);
port ( a : in std_logic_vector((n-1) downto 0);
b : in std_logic_vector((n-1) downto 0);
c : out std_logic_vector((n-1) downto 0));
end component;

signal a std_logic_vector((n-1) downto 0);

signal b std_logic_vector((n-1) downto 0);

signal c std_logic_vector((n-1) downto 0);

begin

U : adder generic map(8);

port map (a,b,c);

(其余略)

end test _bench ;

这不对啊，应该怎么写呢？