我想编一个加法器和减法器集成的程序，但似乎掉用元件的语句属于并行，而process是串行的，怎么处理呢，我需要一个if来作筛选

library ieee;
use ieee.std_logic_1164.all;
entity plus is
port(
judge: in std_logic;
oper1,oper2:in std_logic_vector(3 downto 0);
result1,result2ut std_logic_vector(3 downto 0);
rout1,rout2ut std_logic);
end entity plus;
architecture a of plus is
component adder
port(
a,b:in std_logic_vector(3 downto 0);
sut std_logic_vector(3 downto 0);
coutut std_logic);
end component;
component minus
port(
a,b:in std_logic_vector(3 downto 0);
sut std_logic_vector(3 downto 0);
coutut std_logic);
end component;
begin
u1:adder port map(a=>oper1,b=>oper2,s1=>result,cout1=>rout);
u1:minus port map(a=>oper1,b=>oper2,s2=>result,cout2=>rout);
end a;

[此贴子已经被作者于2008-10-10 13:14:39编辑过]