大侠好：

我用QUARTUS7.2打开原来用QUARTUS4.2生成的工程，然后运行SOPC Builder， 提示要升级sopc_ezCyc.ptf 到 sopc_ezcyc.sopc。升级后提示很多错误，如下图所示。我该怎么解决，谢谢了！！！！！！！！

Info: ext_flash: Flash memory capacity: 2.0 MBytes (2097152 bytes).
Warning: high_res_timer: Period validation cannot be done because input clock is unknown.
Warning: sys_clock_timer: Period validation cannot be done because input clock is unknown.
Error: sdram: Unknown input clock frequency. Please specify the input clock frequency.
Error: sdram: Calculated CAS latency is 0 ns.
Warning: uart1: Baud rate validation cannot be done because the UART's input clock rate is unknown.
Warning: uart2: Baud rate validation cannot be done because the UART's input clock rate is unknown.
Error: /tri_state_bridge_0.clk: Connection dangling at start
Error: /epcs_controller.clk: Connection dangling at start
Error: /ext_flash.clk: Connection dangling at start
Error: /high_res_timer.clk: Connection dangling at start
。。。

Error: /jtag_uart.clk: Connection dangling at start
Error: /cpu_ez.clk: Connection dangling at start
Error: /onchip_ram.clk1: Connection dangling at start
Error: /DA_DATABUS_16BIT.clk: Connection dangling at start
Error: /button_pio.clk: Connection dangling at start
Error: /led_pio.clk: Connection dangling at start
Error: /pio_0.clk: Connection dangling at start
Error: /sdram.clk: Connection dangling at start
Error: /sysid.clk: Connection dangling at start
Error: /uart1.clk: Connection dangling at start
Error: /uart2.clk: Connection dangling at start

可能是这个原因，导入老的文件后，SOPC右上角的clk时钟需要ADD。加入后就没有那些错误了