我是一名初学者，用cadence画的原理图，DRC检错什么的都通过了，也生成了网络表格，但是不能导入pcb edit 中。导入时错误如下希望高人指点)

C) Copyright 2002 Cadence Design Systems, Inc.

------ Directives ------

RIPUP_ETCH FALSE;
RIPUP_SYMBOLS ALWAYS;
MISSING SYMBOL AS ERROR FALSE;
SCHEMATIC_DIRECTORY 'E:/作业/老师给的资料/1/allegro';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'E:/作业/老师给的资料/1/allegro/unnamed.brd';
NEW_BOARD_NAME 'E:/作业/老师给的资料/1/allegro/unnamed.brd';

CmdLine: netrev -$ -5 -i E:/作业/老师给的资料/1/allegro -y 1 E:/作业/老师给的资料/1/allegro/#Taaaaaa02792.tmp

------ Preparing to read pst files ------

Starting to read E:/作业/老师给的资料/1/allegro/pstchip.dat
Finished reading E:/作业/老师给的资料/1/allegro/pstchip.dat (00:00:00.00)
Starting to read E:/作业/老师给的资料/1/allegro/pstxprt.dat
Finished reading E:/作业/老师给的资料/1/allegro/pstxprt.dat (00:00:00.01)
Starting to read E:/作业/老师给的资料/1/allegro/pstxnet.dat
Finished reading E:/作业/老师给的资料/1/allegro/pstxnet.dat (00:00:00.00)

------ Oversights/Warnings/Errors ------

#1 ERROR(302) Device library error detected.

Problems with device 'RESISTOR_AXIAL-0.5_10K'. JEDEC_TYPE property 'AXIAL-0.5' is illegal: 'Package name has invalid characters or is too long.'.

Device 'RESISTOR_AXIAL-0.5_10K' has library errors. Unable to transfer to Allegro.

------ Summary Statistics ------

#2 ERROR(102) Run stopped because errors were detected

netrev run on Nov 29 16:08:22 2008
DESIGN NAME : 'PLC1'
PACKAGING ON Jun 17 2005 00:56:10

COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON

2 errors detected
No oversight detected
No warning detected

cpu time 0:00:09
elapsed time 0:00:00

90

等答案中.

更新原理图版本，部分报告有device错误的器件，重现画下，修改下

另外，项目路径尽量不要有中文