用的器件是XC5VLX50T-FF1136, DDR2 :MT4HTF3264HY-53E

用MIG2.1生成控制器,并根据自己的管脚修改了UCF和顶层的HDL. 在用ISE10.1 MAP 的时候出现下面的错误,请高手指教如何解决.

1.ERROR:place:901-IO Clock Net "u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs[7]" cannont possibly be routed to component "u_ddr2_top/u_men_if_top/u_phy_top/u_phy_io/gen_dq[62].u_iob/stg1_out_fall_2s" (placed in clock regin"CLOCKREGIN_X1Y0"), Since it is too far away from soure BUFIO
"u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_bufio_dqs"(placed in clock regin"CLOCKREGIN_X1Y1"). The situation may be caused by user constraints, or the complxity of the design. Constraining the components related to the regional clock properly may guide the tool to find a solution.
To debug your design with partially routed design, please try to allow MAP/PLACER tofinish the execution (by setting environment variable XI_PAR_DEBUG_IOCLKPLACER to 1).

2.ERROR: pack:1654_The timing_driven packing phase encountered an error.

出现上面两个问题,请高手指教.
还有,就是不知道Xilinx用没有相关的解决错误的资料,比如知道错误代码(如place:901 等)可以找到问题可能出现的原因和解决的办法??