今天做时序约束时，为了观测setup/hold时间,约束条件比较苛刻，故意使setup/hold要求不满足，但在analyze post-place& route static time分析报告里发现奇怪的问题，程序里只使用一个寄存器，但分析setup和hold时间，每个部分的datapath和clockpath居然不一样，按照理解，从clk或者data到这个寄存器只有一个物理通道，这些延迟也只有一个，不知何故？下面是时序报告，请大侠指教！！

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Timing constraint: COMP "a" OFFSET = IN 0.5 ns VALID 0.5 ns BEFORE COMP "clk";

1 item analyzed, 2 timing errors detected. (1 setup error, 1 hold error)
Minimum allowable offset is 0.737ns.
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Slack: -0.237ns (requirement - (data path - clock path - clock arrival + uncertainty))
Source: a (PAD)
Destination: ov (FF)
Destination Clock: clk_buf rising at 1.250ns
Requirement: 0.500ns
Data Path Delay: 3.163ns (Levels of Logic = 1)
Clock Path Delay: 1.176ns (Levels of Logic = 3)
Clock Uncertainty: 0.000ns
Timing Improvement Wizard
Data Path: a to ov
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tiopi 1.726 a
U0IBUF
net (fanout=1) 1.055 a_buf
Tdick 0.382 ov
---------------------------- ---------------------------
Total 3.163ns (2.108ns logic, 1.055ns route)
(66.6% logic, 33.4% route)

Clock Path: clk to ov
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tiopi 1.466 clk
Udcm_1/CLKIN_IBUFG_INST
net (fanout=1) 0.577 Udcm_1/CLKIN_IBUFG_OUT
Tdcmino -2.404 Udcm_1/DCM_SP_INST
net (fanout=1) 0.319 Udcm_1/CLK90_BUF
Tgi0o 1.166 Udcm_1/CLK90_BUFG_INST
net (fanout=1) 0.052 clk_buf
---------------------------- ---------------------------
Total 1.176ns (0.228ns logic, 0.948ns route)

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Hold Paths: COMP "a" OFFSET = IN 0.5 ns VALID 0.5 ns BEFORE COMP "clk";
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Slack (hold path): -0.559ns (requirement - (clock path + clock arrival + uncertainty - data path))
Source: a (PAD)
Destination: ov (FF)
Destination Clock: clk_buf rising at 1.250ns
Requirement: 0.000ns
Data Path Delay: 2.462ns (Levels of Logic = 1)
Clock Path Delay: 1.771ns (Levels of Logic = 3)
Clock Uncertainty: 0.000ns
Timing Improvement Wizard
Data Path: a to ov
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tiopi 1.466 a
U0IBUF
net (fanout=1) 0.844 a_buf
Tckdi (-Th) -0.152 ov
---------------------------- ---------------------------
Total 2.462ns (1.618ns logic, 0.844ns route)
(65.7% logic, 34.3% route)

Clock Path: clk to ov
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tiopi 1.726 clk
Udcm_1/CLKIN_IBUFG_INST
net (fanout=1) 0.721 Udcm_1/CLKIN_IBUFG_OUT
Tdcmino -2.592 Udcm_1/DCM_SP_INST
net (fanout=1) 0.398 Udcm_1/CLK90_BUF
Tgi0o 1.457 Udcm_1/CLK90_BUFG_INST
net (fanout=1) 0.061 clk_buf
---------------------------- ---------------------------
Total 1.771ns (0.591ns logic, 1.180ns route)