调用modelsim仿真时出现下列问题：

# ** Error: D:/Xilinx/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/hdl/vhdl/jtagppc_cntlr.vhd(72): Library unisim not found.
# ** Error: D:/Xilinx/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/hdl/vhdl/jtagppc_cntlr.vhd(73): (vcom-1136) Unknown identifier "unisim".
# ** Error: D:/Xilinx/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/hdl/vhdl/jtagppc_cntlr.vhd(78): VHDL Compiler exiting
# ** Error: d:/modelsim6.2/win32/vcom failed.
# Error in macro ./system.do line 49
# d:/modelsim6.2/win32/vcom failed.
# while executing
# "vcom -93 -work jtagppc_cntlr_v2_00_a "D:/Xilinx/hw/XilinxProcessorIPLib/pcores/jtagppc_cntlr_v2_00_a/hdl/vhdl/jtagppc_cntlr.vhd""

请问这是怎么回事？

是不是我编译的库的问题？我在编译库时提示有错误。请各位帮忙解答一下，谢谢啦

[此贴子已经被作者于2009-5-16 11:27:35编辑过]