各位高手，我自己用verilog在xilinx中编了一段跑马灯程序，可是在板子上运行的时候结果不正确，每次一下载到板子上以后所有的led等就都亮了，程序如下，请多指教啊！
module liushuideng(clk,leds);
input clk;
output[7:0] leds;
reg[3:0] count;
reg[7:0] leds;
initial begin
count=0;
end
always @(posedge clk)
if(count==8)
count=0;
else
begin
case(count)
0: begin
leds=8'b00000001;
#1000000000;
end
1: begin
leds=8'b00000010;
#1000000000;
end
2: begin
leds=8'b00000100;
#1000000000;
end
3: begin
leds=8'b00001000;
#1000000000;
end
4: begin
leds=8'b00010000;
#1000000000;
end
5: begin
leds=8'b00100000;
#1000000000;
end
6: begin
leds=8'b01000000;
#1000000000;
end
7: begin
leds=8'h80;
#1000000000;
end
default: leds=8'h00;
endcase
#1000000000;
count=count+1;
end
endmodule
对它的约束文件如下：
NET "clk" TNM_NET = "clk";
NET "clk" LOC = "c9" | IOSTANDARD = LVCMOS33 ;
NET "leds<7>" LOC = "f9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "leds<6>" LOC = "e9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "leds<5>" LOC = "d11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "leds<4>" LOC = "c11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "leds<3>" LOC = "f11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "leds<2>" LOC = "e11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "leds<1>" LOC = "e12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "leds<0>" LOC = "f12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
各位大侠请多多指教！ |
