请教达人：xilinx SPI ip核 master模式 EDK下不工作 SPI, master, xilinx, 模式, EDK

lance1

主要操作：在EDK中设置xps_spi的输入输出（IP2INTC_Irpt ，SCK_O，MISO_I，SPISEL，SPLB_Clk，SS_O）。选用PowerPC作为CPU，移植linux，编写驱动（主要是修改寄存器）
现象：上电加载模块（.ko文件）后，未有SCLK信号，SS_O一直是高电平（即inactive状态）
疑问：不是只要在寄存器设定了他是master，硬件电路就会自动产生SPLB_Clk/C_SCK_RATIO 这个频率的SCLK么，真的不懂了，希望高手赐教啊~

附上mhs：
BEGIN xps_spi
PARAMETER INSTANCE = xps_spi_0
PARAMETER HW_VER = 2.00.b
PARAMETER C_SCK_RATIO = 96
PARAMETER C_BASEADDR = 0x83c18000
PARAMETER C_HIGHADDR = 0x83c1807f
BUS_INTERFACE SPLB = plb
PORT IP2INTC_Irpt = xps_spi_0_IP2INTC_Irpt
PORT SCK_O = xps_spi_0_SCK_O
PORT MISO_I = clk_500k
PORT SPISEL = net_vcc
PORT SPLB_Clk = sys_clk_s
PORT SS_O = xps_spi_0_SS_O
END

驱动中寄存器设置：
#define XSPI_CR_OFFSET  0x60 /* 16-bit Control Register */
#define XSPI_CR_ENABLE  0x02
#define XSPI_CR_MASTER_MODE 0x04
#define XSPI_CR_CPOL  0x00
#define XSPI_CR_CPHA  0x10
#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL)
#define XSPI_CR_TXFIFO_RESET 0x20
#define XSPI_CR_RXFIFO_RESET 0x40
#define XSPI_CR_MANUAL_SSELECT 0x00
#define XSPI_CR_TRANS_INHIBIT 0x100
#define XSPI_CR_LSB_FIRST 0x200  /*little endian*/
#define XSPI_SR_OFFSET  0x64 /* 8-bit Status Register */
#define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
#define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
#define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
#define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
#define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
#define XSPI_TXD_OFFSET  0x68 /* 8-bit Data Transmit Register */
#define XSPI_RXD_OFFSET  0x6c /* 8-bit Data Receive Register */
#define XSPI_SSR_OFFSET  0x70 /* 32-bit Slave Select Register */
#define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
#define XIPIF_V123B_GINTR_ENABLE 0x80000000
#define XIPIF_V123B_IISR_OFFSET  0x20 /* IPIF interrupt status reg */
#define XIPIF_V123B_IIER_OFFSET  0x28 /* IPIF interrupt enable reg */
#define XSPI_INTR_MODE_FAULT  0x01 /* Mode fault error */
#define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
       * disabled */
#define XSPI_INTR_TX_EMPTY  0x04 /* TxFIFO is empty */
#define XSPI_INTR_TX_UNDERRUN  0x08 /* TxFIFO was underrun */
#define XSPI_INTR_RX_FULL  0x10 /* RxFIFO is full */
#define XSPI_INTR_RX_OVERRUN  0x20 /* RxFIFO was overrun */
#define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
#define XIPIF_V123B_RESET_MASK  0x0a /* the value to write */